A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is a flash EEPROM device (also referred to as “flash memory”).
Each nonvolatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased (what has been described in the art as a “flash-erasure”). The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, and EEPROMs, including flash memory, are commonly used in computer systems that require reprogrammable nonvolatile memory.
Two common types of flash memory architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. In the NOR architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word lines and their drains are connected to bit lines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. The data values of memory cells in a selected row are placed on the bit lines based on the application of a current from the connected source line to the connected bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell are connected by rows to word lines. However, each memory cell is not directly connected to a source line and a bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more, where the memory cells in the string are connected together in series, source to drain, between a common source line and a bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors, allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the bitline to the source line through the channel of each memory cell of the connected string, restricted only by the memory cells of each string that are selected to be read. Thereby, the current encoded stored data values of the row of selected memory cells are placed on the bit lines.
Generally, in a flash memory device, a charged floating gate represents one logic state, e.g., a logic “0”, while a non-charged floating gate represents the opposite logic state e.g., a logic “1”. A memory cell of a flash array is programmed by placing the floating gate into one of these charged states. Charges may be injected or written onto the floating gate by any number of methods, including e.g., avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron (CHE) injection. The floating gate may be discharged or erased by any number of methods including e.g., Fowler-Nordheim tunneling.
During a typical erase operation using Fowler-Nordheim tunneling, charges stored on the floating gate are driven out of the floating gate, through the tunnel oxide, and into the source region. This tunneling of electrons may be achieved by applying a relatively low positive voltage (e.g., approximately 5 volts) to the source region and a relatively large negative voltage (e.g., −8 to −12 volts) to the control gate. The substrate is usually grounded and the drain region is usually left floating. These voltages create an electric field between the floating gate and the source region, which induces the electrons previously stored on the floating gate to tunnel through the tunnel oxide to the source region.
Programming of a flash device is typically achieved by biasing with a series of pulses the drain region to a first voltage, relative to the source region, and biasing the control gate to a second positive voltage which is greater than the first voltage. In the absence of any stored charge on the floating gate, this biasing causes the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. The drain-to-source voltage accelerates the electrons through the channel to the drain region where they acquire sufficiently large kinetic energy. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer which separates the floating gate from the channel region. This electric field attracts the electrons and accelerates them toward the floating gate, which is between the control gate and the channel region, by a process known as tunneling. The floating gate then accumulates and traps the accumulated charge. The negative charge that accumulates on the floating gate reduces the strength of the electric field in the tunneling oxide layer to the point where it is no longer capable of accelerating the electrons from the drain side of the channel region.
The accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage of the field effect transistor comprising the source region, drain region, channel region and control gate to increase. If this increase is sufficiently large, the field effect transistor will remain in a nonconductive off state when a predetermined “read” voltage is applied to the control gate during a read operation. In the programmed state, the flash device may be said to be storing a logic 0. Once programmed, the flash device retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time. However, over programming of a flash memory cell can occur when the voltage of the memory cell is driven above the optimal threshold voltage. Over programming can lead to the inaccurate or even inability to read a memory cell during a read cycle.
Reading the flash device is achieved by applying a predetermined read voltage to the control gate, typically via a word line connecting a row of identical flash devices or cells, and applying a positive bias to the drain region, typically via a bit line connecting a column of identical flash cells. If the flash device is programmed, it will not conduct drain current. However, if the flash device has not been programmed (or has been erased), it is conductive. In this conductive state, the flash device may be said to be storing a logic 1. Thus, by monitoring the bit line current, the programmed state (i.e., 1 or 0) of the cells of the flash device can be determined.
As previously noted, pulses are applied to the lines of a memory array during programming. In order to program an individual memory cell, the voltage of the memory cell is raised (i.e., shifted), by the applied bias and bias pulses, to a programming threshold voltage VTH. Memory cells of an array vary in the speed in which they are programmed. Accordingly, the threshold voltage shift of memory cells occurs at varying speeds even though a pulse of the same voltage and width is applied to all of the memory cells of the array. The distribution of the speeds at which the memory cells are programmed follows a typical bell curve. Accordingly, there are memory cells that are slow to program and fast program, as well as those that are neither fast nor slow (i.e., program at an average speed). The wide distribution of programming times may lead to over programming of some of the memory cells. Accordingly, there is a need and desire for a method which provides a tighter programming distribution by allowing more programming control options for a flash memory device.